FIG. 1 shows exemplary blocks of an FPGA (Field Programmable Gate Array) which is a conventional reconfigurable device. The FPGA comprises logic block array 100, input/output blocks 30—y, 31—x, 32—y, 33—x responsible for data input/output outside the chip, peripheral blocks 50—y, 51—x, 52—y, 53—x which mediate both, and programmable wires (for example, 10_11, 10_21, 11_11, 11_12) for programmably connecting between these blocks. Logic block array 100 is a two-dimensional array of logic blocks 1_xy. Here, x, y are integers indicative of the position of each block.
FIG. 1 illustrates logic block array 100 which is comprised of logic blocks in five rows and five columns (i.e., x and y are integers from one to five, respectively), but in general, the size of a logic block array in an FPGA may be arbitrary.
One example of the logic block in FIG. 1 is shown in FIG. 2. Logic block 1 comprises input selectors 7A and 7B for selecting and outputting one signal from programmable wires 10_W and 12_S, functional element 3 for performing logical processing on outputs of input selectors 7A and 7B to output the result, register 4 for temporarily holding the output of functional element 3 in synchronization with a clock signal, programmable switch 5 for interconnecting the output of register 4 and for programmable wires 13_W, 13_E, 14_S, 14_N, and configuration memory 60.
Configuration memory 60 outputs a signal for determining signals selected from a plurality of input signals and output by input selector 7A and input selector 7B; a signal for determining a logical function of functional element 3; and a signal for determining inter-wire connections implemented by programmable switch 5.
Each logic block 1_xy in FIG. 1 has entirely the same structure of FIG. 2. Programmable wire 10_W in FIG. 2 is connected to an adjacent block to the left; programmable wire 10_E is connected to an adjacent block to the right; programmable wire 11-S is connected to an adjacent block below; and programmable wire 11_N is connected to an adjacent block above. Giving logic block 1_11 in FIG. 1 as an example, programmable wire 10_11 in FIG. 1 corresponds to programmable wire 10_W in FIG. 2; programmable wire 10_21 in FIG. 1 to programmable wire 10_E in FIG. 2; programmable wire 11_11 in FIG. 1 to programmable wire 11_S in FIG. 2; and programmable wire 11_12 in FIG. 1 to programmable wire 11_N in FIG. 2, respectively.
Bold arrows in FIG. 1 represent two signal paths 15 and 16 in a test configuration. On signal path 15, a signal is input from input/output block 30_4, and is supplied to all logic blocks through the programmable wires. On signal path 16, a signal is input from input/output block 30_3, and is supplied to all logic blocks through the programmable wires. The signals on both paths 15, 16 are supplied to each logic block, and simultaneously with this, are forwarded to left-hand adjacent blocks.
Bold arrows in FIG. 2 represent a signal path of each logic block 1 in the test configuration. Input selectors 7A, 7B are configured to output signals on paths 16, 15, respectively, while functional element 3 is configured to provide a logic function which should be tested. Further, programmable switch 5 is configured to convey signals on paths 15, 16 to programmable wire 13_E (i.e., forward them).
In the test configuration, by operating the FPGA by one clock, the result of processing signals on paths 15 16 by functional element 3 is preserved in register 4.
FIG. 3 is a diagram showing a transfer configuration of a test scheme of a conventional FPGA. Bold arrows represent signal path 18—y in the transfer configuration. Specifically, logic blocks in each row are connected from left to right in series, and the output of each row is output to input/output block 32—y through peripheral block 52—y. 
Bold arrows in FIG. 4 represent a signal path of each logic block 1 in the transfer configuration. Input selector 7A is configured to output a signal on programmable wire 12_W, while functional element 3 is configured to output the output of input selector 7A as it is. Output 12_E of register 4 is connected to programmable wire 12_W of a left-hand adjacent logic block.
In FIG. 3, in the transfer configuration, registers 4 of the logic blocks on each row are sequentially connected from left to right in a one-to-another connection form. In this configuration, by operating the FPGA N-1 clocks, data in register 4 in each logic block is sequentially transferred to a left-hand adjacent block, and sequentially read out from the input/output block. Here, N is the number of logic blocks included in one row of logic block array 100.
FIG. 5 shows a flow chart of a conventional FPGA test scheme. At first step 500, a plurality of test configurations, test input data input from the input/output block in each test configuration, and one transfer configuration are prepared.
Next, a first test configuration is loaded into the FPGA (steps 505, 510), and the input/output block is applied with first test input data for the first test configuration (steps 515, 530). Next, the FPGA is operated one clock (step 540). In this way, the result of processing the test input data input from the input/output block by the functional element of the logic block, i.e., test result data, enters the registers in the logic blocks.
Next, the transfer configuration is loaded into the FPGA while the test result data is held in the registers (step 550). Next, the FPGA is operated N-1 clocks to read the test result data within the registers of all logic blocks from the input/output block. Simultaneously with the read, the test result data is compared with an expected value to check whether or not a failure exists (step 560). Next, second test input data of the first test configuration is applied to the input/output block (steps 575, 530).
Subsequently, until all test input data of the first test configuration are exhausted (decision 570), step 530 through step 575 are repeated. Next, a second test configuration is loaded into the FPGA (steps 585, 510). Subsequently, until all test configurations are exhausted (decision 580), steps 510 through 585 are repeated.
The conventional example described above is disclosed, for example, in JP-7-198784-A.